1. Field of the Invention
This invention relates to an electrically writable and non-volatile semiconductor memory device or an electrically writable/erasable non-volatile semiconductor memory device.
2. Description of the Related Art
Document 1: "SINGLE TRANSISTOR ELECTRICALLY PROGRAMMABLE MEMORY DEVICE AND METHOD", U.S. Pat. No. 4,698,787, Oct. 6, 1987.
Document 2: "FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION", U.S. Pat. No. 5,077,691, Dec. 31, 1991.
Document 3: "CIRCUIT AND METHOD FOR ERASING EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED CELLS", U.S. Pat. No. 5,122,985, Jun. 16, 1992.
Document 4: "NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE", Japanese Patent Application Kokai No. JP-A-3-219496.
Document 5: "PRESENT SITUATION AND PROSPECT OF FLASH MEMORY", ICD 91-134, 1991.
The nonvolatile semiconductor memory device includes an ultraviolet erase type EPROM (Erasable and Programmable Read Only Memory) and an electrically writable/erasable (hereinafter, referred to as "electrically alterable") EEPROM (Electrically Erasable and Programmable Read Only Memory). In addition, an electrically erasable flash EEPROM has recently been developed. The data stored in the cells of the EPROM can be erased by ultraviolet ray but cannot be electrically erased. Thus the package for the EPROM is required to have a transparent window. In addition, in order to rewrite after it is mounted on a board of a system, it must be once disconnected from the board. This operation is troublesome. The EEPROM is electrically alterable as mounted in a system, but the memory cell generally needs a transistor or a channel region for selective isolation. Thus the area of the memory cell is about twice larger than the EPROM. In order to solve this problem, a flash type EEPROM which is electrically erasable and has a memory cell area equal to that of the EPROM has been developed.
The flash type EEPROM developed in the early stage is described in, for example, the document 1. The document 1 describes a method of electrically writing and erasing and a device structure, using a single memory transistor having a floating gate. In the erasing operation, a high voltage of 10 to 20 volts (V) is applied to the source terminal of the memory cell and a ground potential to the control gate terminal. A high electric field is generated in a thin insulating film between the floating gate and the source terminal. By the Fowler-Nordheim tunneling phenomenon (hereinafter, referred to as "FN injection") electrons are discharged from the floating gate so that the threshold voltage of the memory cell as viewed from the control gate can be reduced. In the writing operation, a voltage of 5 to 10 V is applied to the drain terminal of the memory cell, a high voltage of 10 to 15 V to the control gate, and the source terminal is grounded, thus generating a strongly inverted region on the substrate surface between the drain and source. As a result, hot electrons (hereinafter, referred to as "HE injection") are generated and thus electrons are injected into the floating gate so that the threshold voltage of the memory cell can be increased.
The document 2 and the document 3, pages 4 to 5 describes another erasing method in which a negative voltage (for example, -7 V to -15 V) is applied to the control gate of the memory cell and a power source voltage (for example, 5 V) or ground potential to the source terminal, thus electrons being discharged from the floating gate by the FN injection. In this method, as disclosed in the document 1, a high voltage (for example, 10 to 20 V) is not necessary to be applied to the source terminal and hence a low voltage can be used when rewriting. Also in this method, since the control gate of the memory cell is generally connected to the row decoder as a word line, a voltage of, for example, 0 to 5 V is applied to the control gate of non-selected memory cells so that the FN injection can be prevented from being caused and that the erasing in a unit of word line (namely sector unit) can be performed.
In order to realize the erasing in a sector unit, however, the resistance to writing and erasing disturbance must be strong enough as compared to the flash type erasing as described on page 5 of the document 3. For example, a write disturb time of about 10 milliseconds is enough for the flash type erase method, but a write disturb time of about ten thousand seconds is necessary for the sector unit erasing, in case of providing a guarantee for one million times of rewriting. In this case, the "disturbance" means that in writing, erasing or reading of the selected memory cell, the amount of charge held in the floating gate of the non-selected memory cell, or the threshold voltage of the non-selected memory cell as viewed from the control gate is changed by the voltage applied to the non-selected memory cell. If the disturbance occurs in the write mode, erase mode or read mode, it is called "write disturbance", "erase disturbance" or "read disturbance" respectively. Since the disturbance causes the change of the threshold voltage of non-selected memory cell (usually, a high threshold voltage is changed to decrease by the disturbance but a low threshold voltage is changed to increase by the disturbance), the stored information will be lost if no countermeasure is taken to the disturbance.
In the document 3, the rate in dose of ion to be implanted in the drain is decreased in order to increase the resistance to the disturbance. When the dose rate in the drain is decreased, however, the drain voltage for writing is necessary to be higher, thus making it difficult to realize the rewriting under a low power supply voltage, for example, a single power source of 5 V.